This page highlights the 8-bit adiabatic multiplier that won First Prize in the VLSI Design Contest (Operational Category) of the 38th Design Automation Conference.






Adiabatic Principles

During the operation of conventional CMOS circuitry, charge is transferred between circuit capacitors and fixed power supply voltages. The per-cycle energy consumption of CMOS designs is thus proportional to the product CV^2, where C is the total switched capacitance, and V is the difference between the power and ground voltages. Adiabatic circuitry presents a promising alternative to this approach. The main idea behind adiabatic design is to transfer charge between circuit capacitors and a time-varying power-clock node. This scheme enables the charge transfers to occur in a controlled manner, limiting the currents and thus the dissipation across the active devices. Any undissipated energy stored in circuit capacitance is recycled through an inductor or a network of switched capacitors. Thus, adiabatic circuitry can potentially achieve sub-CV^2 energy dissipation per cycle.

True Single Phase Adiabatic Logic

We have recently developed a dynamic logic family called SCAL-D. With its extremely simple clocking requirements, SCAL-D is geared towards high-speed and low-energy operation. The most characteristic feature of SCAL-D is that it uses a single phase of a sinusoidal power-clock both as an energy source and as a control signal. SCAL-D has several important properties:


To demonstrate the robustness, efficiency, and practicality of our single-phase adiabatic family, we used it to design an 8-bit unsigned multiplier. A block diagram of our design is given below. Our chip includes two 8-bit unsigned multiplier cores with built-in self-test logic, a single-phase power-clock generator, and adiabatic-to-digital converters to enable the observation of critical signals. The multiplier core and self-test circuitry were implemented entirely in SCAL-D. Approximately 75% of the 11,854 transistors in each multiplier make up the multiplier core, with the remaining 25% devoted primarily to the self-test circuitry. In a 0.5um standard CMOS process, total design area is approximately 0.710mm^2, including the multiplier core of 0.470mm^2.


HSPICE simulations of our multiplier with post-layout extracted parasitics demonstrate its correct operation across a broad range of frequencies. Our design dissipates less energy than a voltage scaled, pipelined, static CMOS multiplier that we designed for comparison. While operating in self-test mode at a clock rate of 100MHz, our adiabatic multiplier dissipates approximately 91pJ per operation with a 2.2V peak supply. At 200MHz, it is roughly 4 times more energy efficient than its CMOS counterpart, dissipating only 130pJ per operation with a 2.7V peak supply.


Our multiplier was fabricated in a standard 3-metal, 1-poly, 0.5um CMOS process through MOSIS. We have experimentally validated the correct operation of our chip at frequencies up to 130MHz, limited by the bandwidth of the off-chip interface. Moreover, we have obtained measurements of its power dissipation which correlate well with simulation results under identical operating conditions.


This research was supported in part by the US Army Research Office under Grant No. DAAD19-99-1-0304 and an AASERT Grant No. DAAG55-97-1-0250.