This page highlights ongoing research into Energy-Recovering VLSI at the University of Michigan Advanced Computer Architecture Laboratory.
- Demonstrate the practicality of single-phase energy recovery for low-energy high-speed VLSI design.
- Design testable prototype of nontrivial size and complexity.
- Achieve working first silicon using a conservative design approach.
- Validate simulation results with experimental energy measurements.
- Demonstrate combined operation of integrated power-clock with clock distribution and PMOS energy recovering flip-flop (PTERF).
- Designed and fabricated resonant-clocked energy-recovering ASIC in a 0.25 bulk silicon process.
- Correct operation validated above 300MHz with self-test logic and integrated power-clock generator.
- Measured power dissipation in energy recovering mode up to 2X lower than in conventional (non-energy recovering) mode.
- Objectives were successfully met, demonstrating the potential of energy recovering design for low-energy VLSI.
- Energy Recovering ASIC Design, ISVLSI 2003 ( PPT )
- Energy Recovering Computers, IBM Austin Conference on Energy Efficient Design, February 2003 ( PPT )
- Energy Recovery Design for Low-Power ASICs, SOC 2003 ( PPT )
- Energy Recovering ASIC Design, ISVLSI 2003 ( PDF)
- Energy Recovery Design for Low-Power ASICs, SOC 2003 ( PDF)